1. Field of the Invention
The present invention relates to a DMA controller provided with a trace buffer for storing trace data to assist the debugging of a program or a system, in a semiconductor integrated circuit equipped with a functional module such as a CPU, and a semiconductor integrated circuit provided with the DMA controller.
2. Description of the Prior Art
Conventionally, in a semiconductor integrated circuit provided with a functional module, such as CPU, and a DMA controller, to assist the debugging of a program or a system, a method of tracing addresses and data transmitted by way of a bus connected to both the functional module and the DMA controller is used.
Referring now to FIG. 20, there is illustrated a block diagram showing the structure of terminal equipment and a data collector which implements an example of such a prior art trace method as disclosed in Japanese patent application publication (TOKKAIHEI) No. 2-308345. In the figure, reference numeral 80 denotes a microprocessor, reference numeral 81 denotes an I/O control circuit, reference numeral 82 denotes a DMA controller, reference numeral 83 denotes a memory, reference numeral 84 denotes a data bus, and reference numeral 85 denotes a synchronous circuit. The terminal equipment consists of the microprocessor 80, the I/O control circuit 81, the DMA controller 82, the memory 83, the data bus 84, and the synchronous circuit 85. Furthermore, reference numeral 86 denotes a trace memory, and reference numeral 87 denotes a data display apparatus. The data collector for collecting trace data from the terminal equipment consists of the trace memory 86 and the data display apparatus 87.
In operation, when the I/O control circuit 81 receives a request for data transfer of input data from the microprocessor 80, the I/O control circuit 81 outputs a request signal 88 to the DMA controller 82. In response to the request signal 88, the DMA controller 82 confirms whether or not the data bus 84 is being used by the microprocessor 80, and, if not, outputs a response signal 89 to both the I/O control circuit 81 and the synchronous circuit 85. The DMA controller 82 also outputs a memory write signal 90 to the memory 83 simultaneously. The I/O control circuit 81 outputs data to be transferred to the memory 83 onto the data bus 84 while the response signal 89 is being input thereto. The synchronous circuit 85 latches the data on the data bus 84 in response to a falling edge of the response signal 89, and simultaneously outputs a trace request signal 91 to the trace memory 86 of the data collector and outputs the latched data onto a trace data bus 92. The trace memory 86 writes data on the trace data bus 92 therein in response to the trace request signal 91. When the writing is completed, the trace memory 86 outputs a write end signal 93 to the synchronous circuit 85, and the synchronous circuit 85 stops the output of the trace request signal 91 in response to the write end signal 93. The terminal equipment and the data collector can collect data to be stored in the memory 83 by repeating such a sequence of operations. The collected data is then displayed in the data display apparatus 87.
A problem with a prior art trace method implemented as above is that though it is possible to perform a control operation so that trace data includes no data associated with CPU accesses, the trace data generally includes data associated with transfers by other bus masters and only data associated with an address bus can be extracted, and therefore it is difficult to extract only traced at a associated with the DMA controller. Furthermore, in accordance with the trace method as shown in FIG. 20, though it is possible to extract the trace data associated with the DMA controller 82, when the DMA controller 82 has a lot of channels, it is difficult to trace information on channel transitions. Accordingly, it is very difficult to determine whether or not the allocation of DMA request sources is appropriate on the system level and whether or not the frequency with which DMA requests are made is appropriate.